1. Technical Field
The present disclosure relates to a semiconductor device with improved linear and switching operating modes, to a method for manufacturing the semiconductor device, and to a method for driving the semiconductor device. In particular, the semiconductor device is a power MOSFET provided with a gate region of a planar type and a gate region of a trench type, which can be biased simultaneously by a single biasing terminal to combine the thermal stability of planar technology in the linear area with the switching operating characteristics of trench technology.
2. Description of the Related Art
Power MOSFETs are electronic devices widely used in various electronic systems. Power MOSFET devices with trench-gate terminal, or of a planar type, are available on the market. In power MOSFETs, the control signal is applied to a gate electrode, which is separated from the semiconductor surface by an insulating layer, typically silicon dioxide SiO2. The control signal is basically a biasing voltage. As compared to a bipolar transistor, the power MOSFET is a unipolar device, i.e., conduction of current occurs by transport of majority carriers in the drift region in the absence of injection of minority carriers for operation of a bipolar transistor. As a consequence of this, no significant delay is observable on account of accumulation or recombination of minority carriers during the turn-off phase. The switching speed is hence higher than that of bipolar transistors. This characteristic is particularly useful in circuits operating at high frequency, where the losses due to switching are particularly high.
FIG. 1a shows, in cross-sectional view, a transistor 1, in particular a planar power MOSFET, comprising a silicon substrate 2 with a doping of an N+ type having a front side 2a and a back side 2b. 
Formed above the front side 2a of the substrate 2 is a drift layer 6, made of silicon with a doping of an N− type. The drift layer 6 houses, at a top face 6a of its own, a body region 8, which extends in depth in the drift layer 6 starting from the top face 6a and is obtained by implantation of dopant species of a P type. Formed within the body region 8 is a source region 10 by implantation of dopant species of an N type so as to form a region with a doping of an N+ type, which extends in the body region 8 starting from the top face 6a. The transistor 1 further comprises a metal layer 12 formed on the top face 6a of the drift layer 6, in direct contact with the body region 8 and, partially, with the source region 10. The metal layer 12 is moreover separated from portions of the top face 6a external, in top plan view, to the body region 8 by layers set on top of one another of insulating material 14 and polysilicon 16, which extend in such a way that the polysilicon 16 is electrically insulated both from the top face 6a and from the metal layer 12 by the layers of insulating material 14. A gate region 18 of the transistor 1 is thus formed. Finally, formed on the back side 2b of the substrate 2 is a drain terminal 19, made of metal material in direct electrical contact with the substrate 2.
FIG. 1b shows a chip or die 15 comprising a plurality of transistors 1. The chip 15 of FIG. 1b hence comprises a plurality of gate regions 18. Extending between two gate regions 18 set alongside one another is a respective body region 8, which in turn houses a source region 10. The drain terminal 19 is a terminal common to all the transistors 1.
In use, by appropriately biasing the gate terminals 18, the source regions 10, and the drain terminal 19, a current i1 flows between the source regions 10 and the drain terminal 19.
FIG. 2a shows a transistor 20 with trench-gate terminal, according to one embodiment of the present disclosure. The transistor 20 comprises a substrate 22, made of doped semiconductor material, for example silicon with a doping of an N+ type. The substrate 22 has a front side 22a and a back side 22b. Extending on the front side 22a of the substrate 22 is a structural layer 26 of doped semiconductor material, for example silicon with a doping of an N− type. The structural layer 26 is, for example, grown epitaxially on the substrate 22 and has the function of drift layer.
The structural layer 26 houses a body region 28, with a doping of a P type, which extends in depth in the structural layer 26 starting from the top face 26a. 
Moreover present are source regions 23, with a doping of an N+ type, which extend in the structural layer 26 within the body region 28 and face the top face 26a of the structural layer 26.
The transistor 20 further comprises gate regions 29 formed in respective trenches, which extend in the structural layer 26, starting from the top face 26a towards the substrate 22. Each trench housing a gate region 29 has a depth greater than the thickness of the body region 28 and smaller than the thickness of the structural layer 26.
Each gate region 29 comprises an insulating portion 29a and a conductive portion 29b, arranged with respect to one another in such a way that the conductive portion 29b is insulated from the structural layer 26 by the insulating portion 29a. 
The transistor 20 further comprises a contact-terminal layer 30, made of conductive material, for example metal, which extends above the top face 26a of the structural layer 26, in direct contact with the body region 28 and, at least partially, with the source regions 23. The contact-terminal layer 30 has, in use, the function of source contact of the transistor 20.
The contact-terminal layer 30 is moreover separated from the portions of the gate regions 29 that face the top side 26a of the structural layer 26 by respective insulating regions 31, for example made of borophosphosilicate glass (BPSG), each formed on top of a respective gate region 29.
Finally, extending on the back side 22b of the substrate 22, in direct electrical contact with the substrate 22, is a collector-terminal layer 32 made of conductive material, for example metal.
FIG. 2b shows a chip or die 35 comprising a plurality of transistors 20. The chip 35 comprises a plurality of gate regions 26, and a respective plurality of source regions 23.
When a plurality of transistors 20 is integrated in a single chip 35, usually an edge-termination region is formed, here not shown. The body regions 28 extend with continuity between the gate regions 29 so that each body region 28 borders laterally (in cross-sectional view) on two gate regions 29.
The drain terminal 32 is a terminal common to all the transistors 20. In use, by appropriately biasing the gate terminals 29, the source regions 23, and the drain terminal 32, a current i2 flows between the source regions 23 and the drain terminal 32.
Some applications of power MOSFETs envisage the use of the latter in the so-called linear operating zone. This condition is satisfied when high currents and high voltages are applied simultaneously to the transistor. Also during use in switching mode, power MOSFETs work in the linear zone, in particular during the passage through the Miller region. It is known in the literature that, when a power MOSFET operates in these conditions, it could present an unstable electrothermal behavior (process known as “thermal runaway”), which could lead the transistor into conditions of improper operation, or even to its breakdown. One of the electrical parameters used for assessing the thermal instability of a power MOSFET operating in the linear zone is the temperature coefficient (TC). The temperature coefficient TC is defined as the derivative with respect to the temperature of the drain current Idrain (TC=dIdrain/dT). The value of TC may be negative, zero, or positive. When TC>0, by applying a power pulse, the temperature T increases (the transistor heats up), and also the drain current Idrain increases. A process of thermal runaway is triggered, which brings the transistor to breakdown. Instead, when TC≦0, as the temperature T increases, there is noted a reduction of the drain current Idrain, and the transistor operates in stable conditions. With the progressive reduction in dimensions, latest-generation power MOSFETs (for example, of the type illustrated in FIGS. 1a, 1b and 2a, 2b) handle high powers in small volumes, and are for this reason particularly subject to phenomena of thermal instability.